Assertion list
interrupt (primary) → ReceivesAction

Results from Ascent++: 40
interruptReceivesAction enabled 0.79
interruptReceivesAction disabled 0.73
interruptReceivesAction triggered 0.64
interruptReceivesAction masked 0.63
interruptReceivesAction generated 0.56
interruptReceivesAction blocked 0.53
interruptReceivesAction received by the cpu 0.48
interruptReceivesAction selected 0.47
interruptReceivesAction detected 0.45
interruptReceivesAction fired 0.45
interruptReceivesAction executed 0.45
interruptReceivesAction ignored 0.44
interruptReceivesAction generated by the processor 0.42
interruptReceivesAction held 0.41
interruptReceivesAction masked with the timer interrupt… 0.41
interruptReceivesAction redirected 0.41
interruptReceivesAction serviced 0.40
interruptReceivesAction received 0.39
interruptReceivesAction left open 0.38
interruptReceivesAction handled by interrupt handler 0.38
interruptReceivesAction injected into virtualized cpu 0.38
interruptReceivesAction requested 0.38
interruptReceivesAction allowed 0.37
interruptReceivesAction placed on the queue 0.35
interruptReceivesAction triggered by software 0.35
interruptReceivesAction missed 0.33
interruptReceivesAction generated at the completion of … 0.32
interruptReceivesAction handled via normal path 0.32
interruptReceivesAction associated with the interrupt s… 0.28
interruptReceivesAction prioritized 0.28
interruptReceivesAction scheduled 0.28
interruptReceivesAction classified in 8085 0.25
interruptReceivesAction deasserted 0.25
interruptReceivesAction disabled in the cpu 0.25
interruptReceivesAction identified by number 0.25
interruptReceivesAction registered 0.25
interruptReceivesAction stored in the lapic 0.25
interruptReceivesAction generated by various devices 0.24
interruptReceivesAction transmitted to the microcontrol… 0.18
interruptReceivesAction lost 0.12